Download Logic Gate Simulator for Windows 10 for Windows to this is a Logic Gate Simulation Application. Current bipolar or MOS digital signals. Driver integrated circuits include peripheral and display drivers used inside an equipment. Line Driver and Receiver Integrated Circuits Line driver and receiver integrated circuits are used to transmit digital information from one subsystem or system to another.

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Download Logic Gate Simulator for Windows 10 for Windows to this is a Logic Gate Simulation Application. Modern digital logic ICs are widely available in three basic types: TTL devices (typified by the 74LS00 logic family), “slow” CMOS devices (typified by the “4000” logic family), and “fast” CMOS devices (typified by the 74HC00 and 74AC00 logic families). Digital Logic proprietary interoperable firmware runs on all MCU platform based µFR Series hardware. The reader and the host establish communication through the high-speed FTDI chip direct access. At the core, on the communication level, the device uses a Digital Logic unique proprietary communication protocol.

A PSpiceÒ Tutorial for Demonstrating Digital Logic

Michael G. Giesselmann, Senior Member, IEEE

Abstract - Several new features of the Evaluation version of PSpice are used to generate demonstration examples for teaching digital logic. An important innovation is the ability to display logic levels on the Schematics page for combinatorial logic circuits. Some of the other main features that are being explored in the examples are hierarchical structures and busses. The paper contains many actual screen views. All circuit files that are discussed in the paper, are included on the CD-ROM.

I. Introduction

At Texas Tech University, PSpice is being used throughout the Electrical Engineering Curriculum. Recent advances in the code, that make PSpice a completely integrated electronic design and analysis tool, and the availability of a free evaluation version make PSpice an ideal companion for the students throughout their progression in the curriculum. In the not so distant past, many different incompatible programs were used for different classes, i.e. PSpice for analog electronics, PCAD for circuit boards, B-squared logic for digital logic and Altera for programmable logic. With an integrated package like PSpice, the students can get in in-depth experience with a sophisticated, real world CAD tool. Since the students are exposed to PSpice in many classes in progressive order, they can learn many advanced techniques, which could not be covered, if they were only exposed to a program for one semester. The students are also rewarded in later classes for learning a program well, which is a rare experience in today's short lived commercial software environment, where the only constant seems to be ever shorter upgrade intervals. In addition, a very in depth knowledge of PSpice will be easily portable to other major electronic design environments like Saber etc., which are all structured similarly.

Another important goal, which requires in-depth knowledge is to teach not only the capabilities of a software package, but also the underlying models and limitations, and to teach the proper use of such a tool.

The PSpice schematics editor provides a very powerful and easy to use interface to generate digital circuits. Some of the main features that are being explored in the examples are hierarchical structures and busses, and bias voltage display. Hierarchical structures enable the student to create structured designs with sub-circuits at several levels. Busses are essential to un-clutter the often numerous connections between digital circuits. Bias point display creates the ability to see the results of a simulation of combinatorial logic directly on the screen.

II. Simulation of Combinatorial Circuits

Figure 1 shows a screen-view of the Schematics editor showing all possible input combinations of AND, OR, NAND, NOR, and EXOR gates with two inputs (Filename=Gates.sch). The result of the simulation is directly displayed in the Schematics page after clicking first on the Bias Point Calculation Button and turning on the bias point display.

Figure 1: Schematics screen view showing AND, OR, NAND, NOR, and EXOR gates with termination sub-circuits and logical Bias levels displayed.

In order to force PSpice to perform a Bias point calculation, analog elements need to be inserted into the circuit. This will cause PSpice to add Digital to Analog interface circuits into the netlist. However, these Interface circuits are not shown. The bias point is the starting (DC) initial value of a transient circuit simulation. The resistors shown in Figure 2 (Filename=Term_4.sch) perform this function. However, if the outputs of the gates under investigation were directly terminated with resistors, the Bias Point display would show actual voltage levels instead of the logic levels shown in Figure 1. In order to force PSpice to show Logic levels, the open collector drivers shown in Figure 2 are used.

Figure 2: Termination circuit for logic level display using Bias point calculation.

The logic inputs of the 7407 drivers forces the display of logic levels rather than analog voltage values. During the simulation, the schematic diagram is being translated into a netlist which is passed on to PSpice for simulation. During this process, Analog to Digital interfaces are being inserted between the output of the open collector drivers, and the 10kW pull-up resistors. The complete sub-circuit shown in Figure 2 resides in the hierarchical blocks Term_4x shown in Figure 1.

Figure 3 shows an example of using a more complex circuit like an MSI full adder in a add-subtract circuit and displaying the results directly in Schematics. In Figure 3, (Filename= Add_sub.sch), the circuit on the left is adding two 4-bit binary numbers with Mode=0, whereas the circuit on the right is subtracting the same two 4-bit binary numbers with Mode=1.

Figure 3: Schematics screen view showing Add-Subtract circuit using an MSI adder with termination sub-circuits and logical Bias levels displayed.

Finally, the most complex example provided for combinatorial logic is shown in Figure 4. Here the hardware for a complete 4x4 binary multiplier (Filename= 4x4_mult.sch) is shown. Here six MSI 7483 full adders along with additions logic are used. In order to enable the Bias point calculation and assure the display of logic levels, two terminators like the ones shown in Figure 2 are used. Again, the results of the simulation; the logic levels at all places are directly shown on the Schematics page.

III. Simulation of Sequential Circuits

Drivers Digital-logic Golf Clubs

The analysis of sequential circuits, i.e. Circuits with Flip-Flops must be performed in the time domain of course. Typical basic circuits are counters and shift registers. The first example on sequential logic shows a circuit using a 74160 and a 74162 synchronous decade counter (Filename=160_162.sch).

Figure 4: Schematics screen view showing 4x4 bit multiplier circuit using an MSI adder with termination sub- circuits and logical Bias levels displayed.

Figure 5: Schematics screen view showing 2 synchronous counters with premature reset showing the difference between synchronous and a-synchronous reset.

The difference between the devices is that the 74160 has a asynchronous reset, whereas the 74162 has a synchronous reset. A screen view of the circuit is shown in Figure 5.The asynchronous reset is immediate except for the propagation delay whereas the synchronous reset will be effective at the next positive edge transition of the clock. The result is that with the identical reset circuitry shown in Figure 5, the counter with the asynchronous reset will only count to 5 whereas the counter with the synchronous reset will count to 6. This is shown in the output diagram taken from the Probe post-processor in Figure 6. Note, that the use of a bus for the output of the counter and the placement of a Voltage/Level Marker on the bus will automatically instruct Probe, to represent the result of the count in Hexadecimal form. This is done by an alternate way of data representation and does not require the storage of additional data in the output data file.

Figure 6: Probe screen view showing 2 synchronous counters with premature reset showing the difference between synchronous and asynchronous reset.

Figure 7: Schematics screen view showing top level of 4-bit ripple counter.

The next example shows a 4-bit ripple counter with hierarchical blocks, which expand to JK flip-flop circuits. Figure 7 (Filename=4bit_rip.sch) shows the top level view of the circuit. The second hierarchical JK-Flip-Flop block is selected. Upon double-clicking, it reveals the underlying flip-flop circuit shown in Figure 8 (Filename=JK.sch).

Figure 8: Schematics screen view of JK flip-flop implementation.

The circuit shown in Figure 8 is contained in the file named JK_FF.sch. Only one instance of this file is needed and all four hierarchical blocks shown in Figure 7 refer to the same file. The input/output ports shown in Figure 8 on the left and right side respectively, are called interface ports. These ports connect to the identical named terminals in the hierarchical blocks shown in Figure 7. Figure 9 shows the output of the ripple counter with individual traces and a combined Hexadecimal representation of the output bus. Figure 10 shows the same result of the ripple counter simulation, but with an expanded time scale at the position were the transition between count 7 and 8 takes place. This Figure clearly shows the ripple effect of consecutive flip-flop transitions that give this counter his name.

Figure 9: Output of Ripple Counter with individual traces and combined bus signal.

Figure 10: Output of Ripple Counter with expanded time scale around the transition between count 7 and 8.

Conclusions

This paper has shown, how some of the new features of the Evaluation version of PSpice can be used to simulate digital circuits. One of the salient new features is the Bias point display on the Schematics page, which greatly enhances the treatment of combinatorial Logic. This feature is specifically appreciated by students in a first course on Digital Logic. In the past the students have often been confused about the necessity to perform transient analyses to obtain simulation results of combinatorial circuits. Some of the other main features that are being explored in the examples are hierarchical structures and busses.

References

PSpice Manual Library, Release 8.0, MicroSim Corporation, Irvine, Ca, 92718. Website: https:// microsim.com.

Author Contact Information

Michael G. Giesselmann, https://www.ee.ttu.edu/ee/giesselm.htm.

Department of Electrical Engineering

Texas Tech University, Lubbock, Texas 79409.

Phone: 806-742-3462

FAX: 806-742-1281

E-Mail: MichaelG@coe.ttu.edu.

Author Biography

Michael G. Giesselmann, biography. Michael Giesselmann was born in 1956 in Basel / Switzerland. After school he studied Electrical Engineering at the Technical University of Darmstadt (TUD)/Germany from 1975-1981. From 1981-1986 he worked as a research assistant at TUD and received a Doctoral degree in Electrical Engineering in 1986. In 1986 Dr. Giesselmann joint the faculty of the EE department at Texas Tech University. He is a Senior Member of the IEEE and a member of the Power Electronics Society, the Power Engineering Society, the Industry Applications Society and the Industrial Electronics Society. Within the Industry Applications Society, he is a member of both the Industrial Drives and the Electric Machines Committee. Dr. Giesselmann is very involved and interested in using information age technology in the classroom. He received the University President’s Excellence in Teaching Award in 1995 and is a Charter Member and Executive Council Member of the TTU Teaching Academy since 1997.

In digital electronicsthree-state, tri-state, or 3-statelogic allows an output or input pin/pad to assume a high impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels.

This allows multiple circuits to share the same output line or lines (such as a bus which cannot listen to more than one device at a time).

Three-state outputs are implemented in many registers, bus drivers, and flip-flops in the 7400 and 4000 series as well as in other types, but also internally in many integrated circuits. Other typical uses are internal and external buses in microprocessors, computer memory, and peripherals. Many devices are controlled by an active-low input called OE (Output Enable) which dictates whether the outputs should be held in a high-impedance state or drive their respective loads (to either 0- or 1-level).

The term tri-state^{[1][citation needed]}should not be confused with ternary logic (3-value logic).

Uses[edit]

The basic concept of the third state, high impedance (Hi-Z), is to effectively remove the device's influence from the rest of the circuit. If more than one device is electrically connected to another device, putting an output into the Hi-Z state is often used to prevent short circuits, or one device driving high (logical 1) against another device driving low (logical 0).

Three-state buffers can also be used to implement efficient multiplexers, especially those with large numbers of inputs.^[2]

Drivers Digital-logic Test

Three-state buffers are essential to the operation of a shared electronic bus.

Three-state logic can reduce the number of wires needed to drive a set of LEDs (tri-state multiplexing or Charlieplexing).

Output enable vs. chip select[edit]

Many memory devices designed to connect to a bus (such as RAM and ROM chips) have both CS (chip select) and OE (output enable) pins, which superficially appear to do the same thing. If CS is not asserted, the outputs are high impedance.

The difference lies in the time needed to output the signal. When chip select is deasserted, the chip does not operate internally, and there will be a significant delay between providing an address and receiving the data. (An advantage of course, is that the chip consumes minimal power in this case.)

When chip select is asserted, the chip internally performs the access, and only the final output drivers are disabled by deasserting output enable. This can be done while the bus is in use for other purposes, and when output enable is finally asserted, the data will appear with minimal delay. A ROM or static RAM chip with an output enable line will typically list two access times: one from chip select asserted and address valid, and a second, shorter time beginning when output enable is asserted.

Use of pull-ups and pull-downs[edit]

When outputs are tri-stated (in the Hi-Z state) their influence on the rest of the circuit is removed, and the circuit node will be 'floating' if no other circuit element determines its state. Circuit designers will often use pull-up or pull-down resistors (usually within the range of 1–100 kΩ) to influence the circuit when the output is tri-stated.

The PCI local bus provides pull-up resistors, but they would require several clock cycles to pull a signal high given the bus's large distributed capacitance. To enable high-speed operation, the protocol requires that every device connecting to the bus drive the important control signals high for at least one clock cycle before going to the Hi-Z state. This way, the pull-up resistors are only responsible for maintaining the bus signals in the face of leakage current.

Intel refers to this convention as 'sustained tri-state', and also uses it in the Low Pin Count bus.

Alternatives to a three-state bus[edit]

The open collector input/output is a popular alternative to three-state logic. For example, the I²C bus protocol (a bi-directional communication bus protocol often used between devices) specifies the use of pull-up resistors on the two communication lines. When devices are inactive, they 'release' the communication lines and tri-state their outputs, thus removing their influence on the circuit. When all the devices on the bus have 'released' the communication lines, the only influence on the circuit is the pull-up resistors, which pull the lines high. When a device wants to communicate, it comes out of the Hi-Z state and drives the line low. Devices communicating using this protocol either let the line float high, or drive it low – thus preventing any bus contention situation where one device drives a line high and another low.

Early microcontrollers often have some pins that can only act as an input, other pins that can only act as a push–pull output, and a few pins that can only act as an open collector input/output. A typical modern microcontroller has many three-state general-purpose input/output pins that can be programmed to act as any of those kinds of pins.

A three-state bus is typically used between chips on a single printed circuit board (PCB), or sometimes between PCBs plugged into a common backplane.

Usage of three-state logic is not recommended for on-chip connections but rather for inter-chip connections.^[3]

Three-state buffers used to enable multiple devices to communicate on a data bus can be functionally replaced by a multiplexer.^[4] That will help select output from a range of devices and write one to the bus.

See also[edit]

Drivers Digital-logic Drivers

Notes and references[edit]

1. ^Tri-state is a registered trademark of National Semiconductor but is often used to describe devices made by any manufacturer.
2. ^Hill, Winfield; Horowitz, Paul (1989). The Art of Electronics. Cambridge University Press. pp. 495–497. ISBN0-521-37095-7.
3. ^경종민, On-Chip Buses/Networks for SoC 'On-Chip Buses [have] No use of tri-state signals [because] Tri-state bus is difficult for static timing analysis'
4. ^'Tri State Buffer'.

Drivers Digital-logic Xerox

External links[edit]

• Special-output Gates on All About Circuits

Case Logic Drivers